Ниxpeна не пойму реальные размеры кэшей (L1, L2, L3)

# cat /proc/cpuinfo | grep cache  

       cache size    : 2048 KB
       cache_alignment    : 64

# dmidecode

Handle 0x0005, DMI type 7, 19 bytes
Cache Information
        Socket Designation: L1-Cache
        Configuration: Enabled, Not Socketed, Level 1
        Operational Mode: Write Back
        Location: Internal
        Installed Size: 384 kB
        Maximum Size: 384 kB
        Supported SRAM Types:
                Pipeline Burst
        Installed SRAM Type: Pipeline Burst
        Speed: 1 ns
        Error Correction Type: Multi-bit ECC
        System Type: Unified
        Associativity: 2-way Set-associative

Handle 0x0006, DMI type 7, 19 bytes
Cache Information
        Socket Designation: L2-Cache
        Configuration: Enabled, Not Socketed, Level 2
        Operational Mode: Write Back
        Location: Internal
        Installed Size: 8192 kB
        Maximum Size: 8192 kB
        Supported SRAM Types:
                Pipeline Burst
        Installed SRAM Type: Pipeline Burst
        Speed: 1 ns
        Error Correction Type: Multi-bit ECC
        System Type: Unified
        Associativity: 16-way Set-associative

Handle 0x0007, DMI type 7, 19 bytes
Cache Information
        Socket Designation: L3-Cache
        Configuration: Enabled, Not Socketed, Level 3
        Operational Mode: Write Back
        Location: Internal
        Installed Size: 6144 kB
        Maximum Size: 6144 kB
        Supported SRAM Types:
                Pipeline Burst
        Installed SRAM Type: Pipeline Burst
        Speed: 1 ns
        Error Correction Type: Multi-bit ECC
        System Type: Unified
        Associativity: 64-way Set-associative

CPU-World https://www.cpu-world.com/CPUs/Bulldozer/AMD-Opteron%20...

Level 1 cache size       4 x 64 KB instruction caches; 8 x 16 KB data caches
Level 2 cache size       4 x 2 MB
Level 3 cache size    8 MB

AMD https://www.amd.com/en/product/1516

L1 Cache 384KB
L2 Cache 8MB
L3 Cache 8MB

$ gcc -### -march=native /usr/include/stdlib.h

--param "l1-cache-size=16" --param "l1-cache-line-size=64" --param "l2-cache-size=2048"